This application claims the priority of Korean Patent Application No. 2002-61788, filed Oct. 10, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a constellation mapping apparatus, which has a simpler structure by using a small-sized memory and a simple decoding circuit and is capable of processing a plurality of constellations, and more particularly, to a constellation mapping apparatus, which can be used in a quadrature amplitude modulator for data communications and can be applied to high-speed data communications using home telephone lines.
2. Description of the Related Art
As the Internet has come into wide use, research has been vigorously carried out on high-speed data communications using home telephone lines. In order to realize a high data transmission speed, a quadrature amplitude modulation (QAM) method has been widely adopted. In a communication manner adopting the QAM method, such as an asymmetric digital subscriber line (ADSL) or home phone line network alliance (home PNA), data are transmitted at different speeds depending on the channel state of a telephone line.
In order to vary a data transmission speed depending on the channel state of a telephone line, a quadrature amplitude modulator, capable of processing a plurality of constellation maps, is necessary. A quadrature amplitude modulator transmits a considerable amount of bit information per symbol via a telephone line when the channel state of the telephone line is good. On the other hand, when the channel state of the telephone line is not good, the quadrature amplitude modulator transmits a small amount of bit information per symbol via the telephone line. In other words, the quadrature amplitude modulator is capable of transmitting data at both high and low speeds through constellation mapping, depending on the channel state of a telephone line.
In home PNA, for example, 2-8 bit data per symbol are transmitted through 7 different constellations, i.e., a quadrature-phase shift keying (QPSK) constellation, an 8-QAM constellation, a 16-QAM constellation, a 32-QAM constellation, a 64-QAM constellation, a 128-QAM constellation, and a 256-QAM constellation. In such home PNA using a plurality of constellations, a memory having a very large storage capacity is necessary to bit-map constellations having different sizes. In addition, a circuit, which is capable of controlling or interpreting input data so that the input data can be mapped in an appropriate constellation corresponding to a desired data transmission speed, is also necessary.
FIG. 1 is a block diagram of a conventional constellation mapping apparatus. Referring to FIG. 1, a conventional constellation mapping apparatus includes a serial to parallel converter 110, an address computation block 120, and a ROM 130 where a look-up table is stored.
The serial to parallel converter 110 converts serial data input thereinto into parallel data and transmits the parallel data to the address computation block 120.
The address computation block 120 generates constellation addresses using bits-per-symbol information and data input thereinto and outputs the constellation addresses in the manner of a look-up table.
Specifically, the address computation block 120 selects a constellation among a plurality of constellations, i.e., an n-QAM constellation (here n is 4, 8, 16, 32, . . . , 2number of input bits) based on bits-per-symbol information. For example, in the case of processing constellations ranging from a 4-QAM constellation to a 256-QAM constellation, the bits-per-symbol information can be represented by 3 bits, since there are 7 constellations between a 4-QAM constellation and a 256-QAM constellation. Therefore, when the bits-per-symbol information has a value of 001, the address computation block 120 selects a 4-QAM constellation. When the bits-per-symbol information is 111, the address computation block 120 selects a 256-QAM constellation.
The ROM 130 stores a look-up table where the constellation addresses generated by the address computation block 120 are stored.
FIG. 2 is a diagram illustrating a 4-QAM constellation and a 16-QAM constellation. Referring to FIG. 2, in the case of a constellation mapping apparatus, which processes 4 QAM and 16 QAM, bits-per-symbol information can be represented by 1 bit. Accordingly, when the value of the bits-per-symbol information is ‘0’, it represents 4 QAM, and when the value of the bits-per-symbol information is ‘1’, it represents QAM. Input data converted into parallel data may be represented by 4 bits. In the case of a 4-QAM constellation, there exist 4 constellation points while in the case of a 16-QAM constellation, there exist 16 constellation points. Accordingly, a ROM, which stores such constellation points, stores 20 words for representing 20 constellation points for in-phase components and quadrature-phase components.
FIG. 3 is a diagram illustrating the structure of a memory for performing constellation mapping. Referring to FIG. 3, an address computation block generates 4 QAM addresses using parallel input data when bits-per-symbol information is ‘0’. On the other hand, when the bits-per-symbol information is ‘1’, the address computation block generates 16 QAM addresses using the parallel input data. Accordingly, if 1 word is represented by 8 bits in the case of processing constellations ranging from a 4-QAM constellation to a 256-QAM constellation, a ROM having a very large storage capacity, for example, a storage capacity of about 1 Kbyte (512 bytes×2), is necessary.